This invention relates in general to the field of electronic devices and more particularly to a system and method for avoiding plasma etch damage.
As device geometries of integrated electronic systems become smaller, the parasitic capacitances of metal interconnects become a more stringent limiting factor than the ability to create smaller geometry features within active devices. A conductive interconnect in an integrated device exhibits a time delay which is related to the resistance and capacitance of the interconnect. One approach to reducing this time delay is to use higher conductive connectors composed of copper instead of aluminum. A separate but non-exclusive approach is to reduce the dielectric constant of the insulative materials adjacent to the interconnects by using materials other than the traditional silicon dioxide. This class of materials is generally referred to as low-K (the preferred term in this invention) or Low-E materials and typically exhibits dielectric constants less than 4.2.
The use of low-K materials presents problems during the processing of the conductive material used to make the interconnects. The conductive material is typically patterned and etched using high energy plasma etch processes. In other process schemes, the low-K material is patterned through the application and patterning of photoresist. The low-K material is etched through the photoresist mask, and then the photoresist removed with a high energy plasma etch process. The low-K materials are susceptible to damage from a plasma etch because they are softer, less chemically stable or more porous, or any combination of these factors. The plasma damage can manifest itself in higher leakage currents, lower breakdown voltages, and changes in the dielectric constant associated with the low-K dielectric material.
Accordingly, a need has arisen for a method of processing which addresses the damage to the low-K dielectric materials during the etching of either the conductive layers or photoresist in immediate contact with the low-K material. In accordance with the teachings of the present invention, a method and device architecture are provided that substantially eliminate or reduce problems associated with prior systems and methods.
According to one embodiment of the present invention, an electronic device is provided that comprises a dielectric layer having a low dielectric constant. A conductive sheath layer is disposed adjacent to the dielectric layer. The conductive sheath layer is operable to electrically divert etchant particles used in a plasma etch process away from the dielectric layer.
In another embodiment of the disclosed invention, a method is provided which comprises covering an inner layer with a layer of dielectric material. The method also comprises depositing a conductive sheath layer outwardly from the layer of dielectric material. A photoresist layer is then deposited outwardly from the conductive sheath layer. The photoresist layer is then patterned resulting in a patterned mask composed of portions of the photoresist layer disposed outwardly from the conductive sheath layer. Portions of the conductive sheath layer not covered by the patterned mask are etched using a plasma etch process selective to the conductive sheath layer relative to the photoresist layer. Portions of the dielectric layer not covered by the patterned mask are also etched using a plasma etch process selective to the dielectric layer relative to the photoresist layer. The photoresist layer is then removed from the conductive sheath layer, the conductive sheath layer providing mechanical and electrical shielding for the dielectric layer.
The disclosed invention provides several technical advantages. For example, the invention provides a process whereby damage to underlying dielectric material is substantially eliminated during the etch of overlying conductive interconnect material. A further advantage of the disclosed invention is that of preventing damage to underlying dielectric material during a resist ash process whereby the photoresist material used to pattern the dielectric layer is removed. Additionally, the invention prevents changes in the dielectric constant of the dielectric material, reduction in the breakdown voltage of the dielectric material, and higher leakage currents across the material to form parasitic electronic devices between conductive vias, for example. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.